Because of these features, there are advantages such as saving space in offices and homes and reducing eye fatigue even when viewed for a long time. However, as higher resolution images are required, the data size per image frame inevitably increases. Accordingly, the operating frequency of the driver driving the flat display device is also increased.
The LCD includes a TFT LCD panel , a source driver array composed of a plurality of source drivers, a gate driver array composed of a plurality of gate drivers, a power supply unit , and a timing controller At the same time, the timing controller outputs a vertical synchronization signal to the gate driver array and outputs a horizontal synchronization signal to the source driver array and the gate driver array In the following description, the control signals for the source driver array and the gate driver array are referred to as a source control signal and a gate control signal, respectively, as shown in FIG.
Display data to be displayed on the TFT LCD panel is first input to the timing controller , and then transmitted to the source driver array via the timing controller The source driver array is composed of n source drivers to n.
The timing controller is connected to each of the source drivers to n, and supplies a start pulse signal DIO1, an operation clock signal CLK, a display data signal DATA, and a horizontal latch signal LD to each of the source drivers to n as shown in FIG. To do. The operation clock signal CLK, the display data signal DATA, and the horizontal latch signal LD are transmitted on the same bus, and the source drivers to n are connected to the bus to receive these signals.
Next, the start pulse signal DIO1 is connected in a one-to-one manner, is latched according to the operation clock signal CLK, and functions as a control signal when the data signal DATA is sequentially distributed. When the line buffer is full in the data latch unit, the source driver outputs a start pulse signal DIO2 and supplies it to the next active source driver.
By using data by this method in a serial sequence, the image can be enlarged. The DAC is connected to the gamma voltage generation circuit The start pulse signal DIO1 is latched and serves as a control signal for sequentially distributing data.
The display data signal DATA is then transmitted to the sampling register via the data latch unit and the data bus. The hold register also receives a horizontal latch signal LD. After the level shift unit adjusts the voltage of the display data signal, the signal is transmitted to the DAC A gamma voltage is input to the gamma voltage generation circuit from the outside, and an output is exported to the DAC according to the gamma voltage, and this output becomes a reference for adjusting the analog signal.
For this reason, a latch error of the start pulse signal is likely to occur, and therefore the maximum operating frequency is limited. The current method can be realized only up to about MHz. As shown in FIG. At time T2, the source driver receives the start pulse signal DIO1, latches it according to the operation clock signal CLK, and sets it as a control signal for sequentially distributing data. When the line buffer of the data latch unit becomes full, the source driver transmits a start pulse signal DIO2 to be used by the next source driver, for example, at time T3.
Such sequential transmission continues until the display data of one horizontal line is completely latched. At this time, the timing controller outputs a horizontal latch signal LD to convert the data in the line buffer from digital to analog, and then the gray level voltage is exported to the TFT LCD panel. This solves the conventional problem that the maximum operating frequency of the panel display driver due to the start pulse signal is limited.
In addition, for example, a configuration including two buses can reduce the extra cost required to increase the operating frequency while maintaining the conventional method.
This source driver receives display timing information from the timing controller. The source driver has a start pulse generation circuit used to receive the position code signal, generates a start pulse signal based on the position code signal, and controls data distribution of the display data signal in the display timing information. Function as a signal. Then, after the counted value becomes the same as the source driver encoded signal POS , reception of the display data signal in the display timing data is started.
K is defined as the number of data to be latched by the source driver. The number of data to be latched by the source driver refers to the number of output channels of the source driver.
Is converted to analog and the data is exported to the display panel of the display device. The start code detection circuit receives display timing data transmitted from the timing controller and is used to detect whether the display timing data includes a horizontal latch signal. When the horizontal latch signal is detected, it is further detected whether or not the display data signal of the display timing data includes a start code, and a permission signal is generated according to the result.
The synchronization counter is connected to the start code detection circuit, and receives a permission signal, a horizontal latch signal, and an operation clock signal. Of these, the horizontal latch signal resets the synchronization counter to 0, and the synchronization counter follows the permission signal.
Resume counting. The decoding circuit is used to receive the position code signal and generates a source driver encoded signal POS accordingly. The digital comparator is connected to the synchronization counter and the decoding circuit, and compares the value of the source driver encoded signal POS with the value of the synchronization counter.
If the count values are the same, reception of the display data signal of the display timing data is started. This source driver array is composed of a plurality of source drivers, and each of the plurality of source drivers is connected to a timing controller and receives display timing data. Each of the plurality of source drivers receives a corresponding position code signal. At this time, the position code signal corresponding to each source driver is determined according to the driving sequence of the plurality of source drivers in the source driver array.
In accordance with the position code signal, a signal for controlling data distribution of the display data signal in the display timing data is transmitted to the display panel. The source driver array is composed of a plurality of source drivers. The timing controller is connected to each of the plurality of source drivers and supplies display timing data to each source driver.
Each source driver receives a corresponding position code signal. The position code signal corresponding to each source driver is determined according to the driving sequence of the plurality of source drivers of the source driver array. Used as a signal to control data distribution. This drive circuit includes a timing controller and a source driver array. The timing controller is connected to each of the plurality of source drivers and supplies display timing information to the individual source drivers.
The present invention provides the following advantages. The simple source characteristics that coincident source driver array arrays promise are an attractive design goal but many engineering obstacles must be overcome to avoid undesirable complex behaviour. Click to purchase paper as a non-member or login as an AES member.
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